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a u s t ri a m i c r o s y s t e m s
A S 11 5 0 , A S 11 5 1 Q u a d LV D S R e c e i v e r s
D a ta S he e t
1 General Description
The AS1150 and AS1151 are quad flow-through LVDS (low-voltage differential signaling) receivers which accept LVDS differential inputs and convert them to LVCMOS outputs. The receivers are perfect for lowpower low-noise applications requiring high signaling rates and reduced EMI emissions. The devices are guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlled impedance media of approximately 100. Supported transmission media are PCB traces, backplanes, and cables. The AS1150 uses high impedance inputs and requires an external termination resistor when used in a point-topoint connection. The AS1151 features integrated parallel termination resistors (nominally 107), which eliminate the requirement for discrete termination resistors, and reduce stub lengths. The integrated failsafe feature sets the output high if the inputs are open, undriven and terminated, or undriven and shorted. Enable inputs (EN and ENn - internally pulled down to GND) control the high-impedance output and are common to all four receivers. All inputs conform to the ANSI TIA/EIA- 644 LVDS standards. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVDS inputs and LVCMOS outputs. The devices are available in a 16-pin TSSOP package. Figure 1. Block Diagrams
VCC
2 Key Features
! ! ! ! ! ! ! ! !
Flow-Through Pinout Guaranteed 500Mbps Data Rate 300ps Pulse Skew (Max) Conform to ANSI TIA/EIA-644 LVDS Standards Single +3.3V Supply Operating Temperature Range: -40 to +85C Failsafe Circuit Integrated Termination (AS1151) 16-pin TSSOP Package
3 Applications
The devices are ideal for digital copiers, laser printers, cellular phone base stations, add/drop muxes, digital cross-connects, dslams, network switches/routers, backplane interconnect, clock distribution computers, intelligent instruments, controllers, critical microprocessors and microcontrollers, power monitoring, and portable/battery-powered equipment.
VCC
IN1+ IN1-
Rx
IN1+ OUT1 IN1-
107
Rx
OUT1
IN2+ IN2-
Rx
IN2+ OUT2 IN2-
107
Rx
OUT2
IN3+ IN3-
Rx
IN3+ OUT3 IN3-
107
Rx
OUT3
IN4+ IN4EN
Rx
IN4+ OUT4 IN4EN
107
Rx
OUT4
ENn
AS1150
ENn
AS1151
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4 Absolute Maximum Ratings
Stresses beyond those listed in Table 1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Section 5 Electrical Characteristics on page 3 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 1. Absolute Maximum Ratings Parameter VCC to GND INx+, INx- to GND EN, ENn to GND OUTx to GND Continuous Power Dissipation (TAMB = +70C) Storage Temperature Range Maximum Junction Temperature Operating Temperature Range ESD Protection -40 -4 -65 Min -0.3 -0.3 -0.3 -0.3 Max +5.0 +5.0 VCC + 0.3 VCC + 0.3 750 +150 +150 +85 +4 Units V V V V mW C C C kV Human Body Model, INx+, INxThe reflow peak soldering temperature (body temperature) specified is in compliance with IPC/JEDEC J-STD-020C "Moisture/ Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". Derate 9.4mW/C Above +70C Notes
Package Body Temperature
260
C
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DC Electrical Characteristics
5 Electrical Characteristics
DC Electrical Characteristics
VCC = +3.0 to +3.6V, Differential Input Voltage |VID| = 0.1 to 1.0V, Common-Mode Voltage VCM = |VID/2| to 2.4V - |VID/2|,TAMB = -40 to +85C. Typical values are at VCC = +3.3V, TAMB = +25C (unless otherwise specified). Table 2. DC Electrical Characteristics Parameter LVDS Inputs (INx+, INx-) Differential Input High Threshold Differential Input Low Threshold Input Current (AS1150) Power-Off Input Current (AS1150) Input Resistor 1 (AS1150) Input Resistor 2 (AS1150) Common Mode Input Resistance Differential Input Resistance VTH VTL IINx+, IINxIINOFF RIN1 RIN2 RINCM RDIFF 0.1V |VID| 0.6V 0.6V |VID| 1.0V 0.1V |VID| 0.6V, VCC = 0 0.6V |VID| 1.0V, VCC = 0 VCC = 3.6V or 0, Figure 16 on page 9 VCC = 3.6V or 0, Figure 16 on page 9 AS1151: Input = 0 AS1151: VCC = 3.6V or 0, Figure 16 on page 9 Open, undriven short, or undriven 100 parallel termination VID = +100mV IOH = -4.0mA (AS1151) Output Low Voltage Output Short-Circuit 2 Current Output High-Impedance Current Logic Inputs (EN, ENn) Input High Voltage Input Low Voltage Input Current Supply Supply Current Disabled Supply Current Notes: 1. Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, and VID. 2. Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. ICC ICCZ Enabled, Inputs Open average value, |VID| = 200mV Disabled, Inputs Open 5 8 300 11 15 500 mA A VIH VIL IIN VINx = VCC or 0 2.0
0 VCC
1 1
1
Symbol
Conditions
Min
Typ
Max
Unit
100 -100 -20 -25 -20 -25 35 132 150 90 107 132 20 25 20 25
mV mV A A A A k k k
LVCMOS/LVTTL Outputs (OUTx) IOH = -4.0mA Output High Voltage (Table 5)
(AS1150)
2.7 2.7 2.7 2.7
3.2 3.2 3.2 3.2 0.1 0.25 160 10 V mA A V
VOH
Open or Undriven Short VID = +100mV
VOL IOS IOZ
IOL = +4.0mA, VID = -100mV Enabled, VID = 0.1V, VOUTx = 0 Disabled, VOUTx = 0 or VCC 15 -10
V V A
0.8 15
-15
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AC Electrical Characteristics
AC Electrical Characteristics
VCC = +3.0 to +3.6V, CLOAD = 15pF, Differential Input Voltage |VID| = 0.2 to 1.0V, Common-Mode Voltage VCM = |VID/2| to 2.4V -|VID/2|, Input Rise and Fall Time = 1ns (20 to 80%), Input Frequency = 100MHz, TAMB = -40 to +85C. Typical values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TAMB = +25C (unless otherwise specified). Table 3. AC Electrical Characteristics Parameter Differential Propagation Delay Highto-Low Differential Propagation Delay Lowto-High
Differential Pulse Skew (tPHLD - tPLHD)
3 1, 2
Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL tPHZ tPLZ tPZH tPZL
7, 8
Conditions Figure 18 on page 11 and Figure 19 on page 12 Figure 18 on page 11 and Figure 19 on page 12 Figure 18 on page 11 and Figure 19 on page 12
Figure 18 on page 11 and Figure 19 on
Min 1.6 1.6
Typ 2.0 2.0 140
Max 3.1 3.1 300 400 0.8 1.5
Unit ns ns ps ps ns ns ns ns ns ns ns ns MHz
Differential Channel-to-Channel 4 Skew Differential Part-to-Part Skew Differential Part-to-Part Skew Rise Time Fall Time Disable Time High-to-Z Disable Time Low-to-Z Enable Time Z-to-High Enable Time Z-to-Low Maximum Operating Frequency Notes: 1. 2. 3. 4. 5. 6. 7.
5 6
page 12 Figure 18 on page 11 and Figure 19 on page 12 Figure 18 on page 11 and Figure 19 on page 12 Figure 18 on page 11 and Figure 19 on page 12 Figure 18 on page 11 and Figure 19 on page 12 RLOAD = 2k, Figure 20 on page 12 and Figure 21 on page 12 RLOAD = 2k, Figure 20 on page 12 and Figure 21 on page 12 RLOAD = 2k, Figure 20 on page 12 and Figure 21 on page 12 RLOAD = 2k, Figure 20 on page 12 and Figure 21 on page 12 All Channels Switching 250 300 0.5 0.5
1.0 1.0 14 14 70 70
fMAX
8.
AC parameters are guaranteed by design and characterization. CL includes scope probe and test jig capacitance. tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|. tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same device. tSKD3 is the magnitude difference of any differential propagation delays between devices operating over rated conditions at the same VCC and within 5C of each other. tSKD4 is the magnitude difference of any differential propagation delays between devices operating over rated conditions. fMAX generator output conditions: a. Rise time = fall time = 1ns (0 to 100%) b. 50% duty cycle c. VOH = +1.3V d. VOL = +1.1V Output criteria: a. Duty cycle = 60% to 40% b. VOL = 0.4V (max) c. VOH = 2.7V (min) d. Load = 15pF
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AC Electrical Characteristics
6 Typical Operating Characteristics
VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CLOAD = 15pF, TAMB = +25C, unless otherwise noted. Figure 2. Supply Current vs. Frequency
100 90
Figure 3. Supply Current vs. Temperature
14
.
80
All Channels Switching
Supply Current (mA)
Supply Current (mA)
.
12 10 8 6 4 2
Outputs Low
70 60 50 40 30 20 10 0 0,01 0,1 1
One Channel Switching
Outputs High
0 10 100 1000 -40 -20 0 20 40 60 80 100
Frequency (MHz)
Tem perature (C)
Figure 4. Diff. Threshold Voltage vs. VCC
70
Figure 5. Output Short-Circuit Current vs. VCC
120
.
Diff. Threshold Voltage (mV)
60
High to Low
50 40 30 20 10 0 3 3,1 3,2 3,3 3,4 3,5 3,6
Low to High
Output Short-Circuit Current (mA) .
100 80 60 40 20 0 3 3,1 3,2 3,3 3,4 3,5 3,6
Supply Voltage (V)
Supply Voltage (V)
Figure 6. Output Low Voltage vs. VCC
110
Figure 7. Output High Voltage vs. VCC
3,7
.
Output Low Voltage (mV)
109
Output High Voltage (V) .
3 3,1 3,2 3,3 3,4 3,5 3,6
3,5
108
3,3
107
3,1
106
2,9
105
2,7 3 3,1 3,2 3,3 3,4 3,5 3,6
Supply Voltage (V)
Supply Voltage (V)
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AC Electrical Characteristics
Figure 8. Differential Propagation Delay vs. VCC
2,2
Figure 9. Differential Propagation Delay vs. Temperature
2,25
.
Diff. Propagation Delay (ns)
Diff. Propagation Delay (ns)
.
2,16 2,2 2,12
tPHLD
2,15
tPLHD
2,08
tPLHD
2,1
tPHLD
2,04
2,05
2 3 3,1 3,2 3,3 3,4 3,5 3,6
2 -45 -25 -5 15 35 55 75 95
Supply Voltage (V)
Tem perature (C)
Figure 10. Differential Propagation Delay vs. VCM
2,5
Figure 11. Differential Propagation Delay vs. VID
2,3
.
Diff. Propagation Delay (ns)
2,4 2,3 2,2
tPHLD
Diff. Propagation Delay (ns)
.
2,2 2,1
tPHLD
2
tPLHD
2,1
tPLHD
2 1,9 -0,5
1,9
1,8
0
0,5
1
1,5
2
2,5
0,1
0,5
0,9
1,3
1,7
2,1
2,5
Common-Mode Voltage (V)
Figure 12. Differential Pulse Skew vs. VCC
80
Differential Input Voltage (V)
Figure 13. Transition Time vs. VCC
400
.
380
75 70 65 60 55 50 45 40 3 3,1 3,2 3,3 3,4 3,5 3,6
.
Diff. Pulse Skew (ps)
Transition Time (ps)
tTLH
360
tTHL
340
320
300 3 3,1 3,2 3,3 3,4 3,5 3,6
Supply Voltage (V)
Supply Voltage (V)
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AC Electrical Characteristics
Figure 14. Transition Time vs. Temperature
500
.
450
Transition Time (ps)
400
tTLH
350
tTHL
300
250 -45 -25 -5 15 35 55 75 95
Tem perature (C)
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Pin Assignments
7 Pinout
Pin Assignments
Figure 15. Pin Assignments (Top View)
IN1IN1+ IN2+ IN2IN3IN3+ IN4+ IN4-
1 2 3 4 5 6 7 8
16 EN 15 OUT1 14 OUT2
AS1150 AS1151
13 VCC 12 GND 11 OUT3 10 OUT4 9 ENn
Pin Descriptions
Table 4. Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name IN1IN1+ IN2+ IN2IN3IN3+ IN4+ IN4ENn OUT4 OUT3 GND VCC OUT2 OUT1 EN Description Inverting Differential Receiver Input Noninverting Differential Receiver Input Noninverting Differential Receiver Input Inverting Differential Receiver Input Inverting Differential Receiver Input Noninverting Differential Receiver Input Noninverting Differential Receiver Input Inverting Differential Receiver Input Receiver Enable Input. Internally pulled down to GND. When EN = high and ENn = low or open, the receiver outputs are active. For other combinations of EN and ENn, the outputs are disabled and in high impedance. LVCMOS/LVTTL Receiver Output LVCMOS/LVTTL Receiver Output Ground Power-Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. LVCMOS/LVTTL Receiver Output LVCMOS/LVTTL Receiver Output Receiver Enable Input. Internally pulled down to GND. When EN = high and ENn = low or open, the receiver outputs are active. For other combinations of EN and ENn, the outputs are disabled and in high impedance.
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LVDS Interface
8 Detailed Description
The AS1150 and AS1151 are 500Mbps, four-channel LVDS receivers intended for high-speed, point-to-point, lowpower applications. Each independent channel accepts and converts an LVDS input to an LVTTL/LVCMOS output. The devices are capable of detecting differential signals from 100mV to 1V within an input voltage range of 0 to 2.4V. The 250 to 450mV differential output of an LVDS driver is nominally centered around 1.25V. Due to the receiver input voltage range, a 1V voltage shift in the signal relative to the receiver is allowed. Thus, a difference in ground references of the transmitter and the receiver, as well as the common mode effect of coupled noise, can be tolerated.
LVDS Interface
The LVDS Interface Standard is a signaling method defined for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, resulting in higher data rates, reduced power consumption and EMI emissions, and less susceptibility to noise. The devices fully comply with the LVDS standard input voltage range of 0 to +2.4V referenced to receiver ground. The AS1151 has an integrated termination resistors connected internally across each receiver input. This internal termination saves board space, eases layout, and reduces stub length compared to an external termination resistor. In other words, the transmission line is terminated on the IC.
Failsafe Circuit
The devices contain an integrated failsafe circuit to prevent noise at inputs that are open, undriven and terminated, or undriven and shorted. Open or undriven terminated input conditions can occur if there is a cable failure or when the LVDS driver outputs are high impedance. A short condition also can occur because of a cable failure. The failsafe circuit of the AS1150/AS1151 automatically sets the output high if any of these conditions are true. The failsafe input circuit (see Figure 16) samples the input common-mode voltage and compares it to VCC - 0.3V (nominal). If the input is driven to levels specified in the LVDS standards, the input common-mode voltage is less than VCC 0.3V and the failsafe circuit is not activated. If the inputs are open, undriven and shorted, or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the failsafe circuit pulls both inputs above VCC - 0.3V, activating the failsafe circuit and thus forcing the device output high. Figure 16. Failsafe Input Circuit
VCC VCC
RIN2
RIN2
VCC - 0.3V INx+ RIN1 OUTx RIN1 INx+ RIN1 RDIFF RIN1
VCC - 0.3V
OUTx
INx-
INx-
AS1150
AS1151
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9 Applications
Table 5. Function Table Enable Pins EN ENn INx+ VID +100mV VID +100mV H L or Open AS1150 - Open, undriven short, or undriven 100 parallel termination AS1151 - Open or undriven short Other Combinations of Enable Pin Settings Figure 17. Typical Application Circuit
LVDS Signals Tx 107 Rx
Input INx-
Output OUTx H L H Z
Don't Care
Tx LVTTL/LVCMOS Data Inputs
107
Rx LVTTL/LVCMOS Data Outputs
Tx
107
Rx
Tx
107
Rx
AS1152 Quad LVDS Driver
AS1151
100 Shielded Twisted Cable or Microstrip PC Board Traces
Power-Supply Bypassing
To bypass VCC, use high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to pin VCC.
Differential Traces
Input trace characteristics can adversely affect the performance of the AS1150 and AS1151.
! ! ! !
Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor must also be matched to this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running differential traces close together. Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper data recovery of the devices. Route each channel's differential signals very close to each other for optimal cancellation of their respective external magnetic fields. Use a constant distance between the differential traces to avoid irregularities in differential impedance. Avoid 90 turns (use two 45 turns). Minimize the number of vias to further prevent impedance irregularities.
! !
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Cables and Connectors
Supported transmission media include printed circuit board traces, backplanes, and cables.
!
Use cables and connectors with matched differential impedance (typically 100) to minimize impedance mismatches. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
!
!
Termination
Due to the high data rates of LVDS drivers, matched termination will prevent the generation of any signal reflections, and reduce EMI.
!
The AS1151 has integrated termination resistors connected across the inputs of each receiver. The value of the integrated resistor is specified in Table 2 on page 3. The AS1150 requires an external termination resistor. The termination resistor should match the differential impedance of the transmission line and be placed as close to the receiver inputs as possible. Termination resistance values may range between 90 to 132 depending on the characteristic impedance of the transmission medium. Use 1% surface-mount resistors.
!
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
! ! !
Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals. Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent coupling. Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
!
Figure 18. Propagation Delay and Transition Time Test Circuit
INx+ Pulse Generator** INx50 50 CL OUT
Receiver Enabled 1/4 AS1150, AS1151
* 50 required for pulse generator. ** When testing the AS1151, adjust the pulse generator output to account for internal termination resistor.
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Figure 19. Propagation Delay and Transition Time Waveforms
INxVID = 0 INx+ tPLHD tPHLD VOH VID = (VINx+) - (VINx-) Note: VCM = (VIN- + VIN+) 2 80 80 VID VID = 0
50% 20 OUTx tTLH
50% 20 tTHL VOL
Figure 20. High Impedance Delay Test Circuit
VCC S1
INx+ Generator 50 EN ENn INx-
RL Device Under Test OUTx CL
CL includes load and test JIG capacitance. S1 = VCC for tPZL and tPLZ measurements. S1 = GND for tPZH and tPHZ measurements.
Figure 21. High Impedance Delay Waveforms
EN when ENn = GND or Open 1.5V 1.5V
3V 0
3V 1.5V ENn when EN = VCC tPZL tPLZ 50% Output when VID = -100mV Output when VID = +100mV 0.5V tPHZ 0.5V 50% GND tPZH VOH VOL VCC 1.5V 0
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Board Layout
10 Package Drawings and Markings
Figure 22. 16-Pin TSSOP Package
Symbol A A1 A2 L R R1 b b1 c c1 D E1 E Notes:
0.65mm Lead Pitch Min Nom Max 1.10 0.05 0.15 0.85 0.90 0.95 0.50 0.60 0.75 0.09 0.09 0.19 0.30 0.19 0.22 0.25 0.09 0.20 0.09 0.16 4.90 4.30 5.00 4.40 6.4 BSC 5.10 4.50
1, 2
Note
Symbol 1 L1 aaa bbb ccc ddd e 2 3
5
0.65mm Lead Pitch Min Nom Max 0 8 1.0 Ref 0.10 0.10 0.05 0.20 0.65 BSC 12 Ref 12 Ref
1, 2
Note
Variations 3, 8 e 4, 8 N
0.65 BSC 16
6
1. All dimensions are in millimeters; angles in degrees. 2. Dimensions and tolerancing per ASME Y14.5M-1994. 3. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15mm per side. 4. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side. 5. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm total in excess of dimension b at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm for 0.5mm pitch packages. 6. Terminal numbers shown are for reference only. 7. Datums A and B to be determined at datum plane H. 8. Dimensions D and E1 to be determined at datum plane H. 9. This dimension applies only to variations with an even number of leads per side. For variations with an odd number of leads per package, the center lead must be coincident with the package centerline, datum A. 10. Cross section A-A to be determined at 0.10 to 0.25mm from the leadtip.
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Board Layout
11 Ordering Information
Model AS1150 AS1150-T AS1151 AS1151-T Description Quad low-voltage differential signaling receiver Quad low-voltage differential signaling receiver Quad low-voltage differential signaling receiver with integrated termination Quad low-voltage differential signaling receiver with integrated termination Package Type 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP Delivery Form Tubes Tape and Reel Tubes Tape and Reel
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Board Layout
Copyrights
Copyright (c) 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com
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